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在中国期刊网prehensive after simulation, and, after the wiring layout simulation, configuration download and debug, and other major steps (1) circuit design and input Circuit Design and the importation of certain norms is through the description, will be input to the circuit concept of EDA tools. Common design input including the use of hardware description language HDL, schematic design and design methods such as state plans. HDL design of the current large-scale digital IC design is a good form, which affected the most widely HDL language is Verilog HDL and VHDL. Their common feature is conducive to top-down design, with the help of the module reuse, portability, and common good, not because of chip design and structure of the different changes conducive to the ASIC transplantation. (2) function simulation Functional simulation is the use of simulation tools for the design has achieved a full test. Verify whether the circuit functions with the design requirements, functional simulation is sometimes known as the former simulation. The simulation can promptly found an error in the design, designed to accelerate progress and improve the reliability of the design. (3) overall optimization Overall optimization is to meet the circuit's bound to be achieved under the conditions, HDL language, schematics and other input into the design and, or, non-door, RAM, flip-flop, and other basic logic modules connect to the logic and then through computer The speed and size of a logic optimization, and the output edf edn standard format, such as the netlist documents, access to meet the requirements of a circuit design. Comprehensive optimized the FPGA netlist documents for the layout and wiring manufacturers carried out to achieve. (4) after the comprehensive simulation Comprehensive after the completion of the need to examine whether the consolidated results consistent with the original design, done after the comprehensive simulation. In simulation, the generation of comprehensive standard-delayed document marked in the comprehensive simulation model to be estimated the impact of delayed door. Comprehensive simulation after the main purpose of inspection is integrated with the combined effect is consistent with the design input. (5) wiring layout Overall optimization of the network scale and the logic chip in the actual configuration There is still a gap. FPGA vendors to provide the use of software tools, according to the selected chip models, the output of logic integrated network adapter to the table specific target FPGA device, called the realization of this process. In the process of achieving the most important is the process of wiring layout: the layout is logical network will be in the form of the original language or the underlying hardware unit to a reasonable fit within the FPGA hardware inherent in the structure, layout design of the merits of the ultimate realization of results Very influential. Wiring is based on the layout of topology, using all kinds of connections within the FPGA resources, a correct and reasonable process of connecting the various components. (6) timing simulation and verification Layout of the wiring delay information to design anti-tagging network in the table, called the simulation conducted by the timing or place and route simulation after simulation, called after the simulation. After the wiring layout generated simulation delay file contains the most full-time delay information that includes not only delay the door, but also the actual wiring delay, after routing the most accurate simulation. After the wiring layout design timing simulation can check with the actual operation of the FPGA line, designed to ensure the reliability and stability. (7) to download configuration, debugging Download configuration means that the timing simulation correct premise, will form the specific configuration files downloaded to the FPGA in. Directly from the computer configuration or cable for downloading from the external configuration on the chip, auto-configuration. The FPGA design is generally carried out in accordance with the above process development, simulation or verification of any problems, on the basis of the wrong location to return to the appropriate steps to make changes or re-design. 中文 » 英语 翻译 更好的翻译建议 感谢您为 Google 翻译提供翻译建议。
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